#--------------------------Specify Macros----------------------------
set_host_options -max_cores 4
#just try ,system may not commit
set HDL verilog
set SYN_ROOT_PATH ../../syn
set TOP_DESIGN top
#--------------------------Specify Libraries--------------------------

source ../scripts/dc_setup.tcl

#--------------------------Prepare Filelist---------------------------
set FILE_LIST ""
set f [open "../filelist_syn.f" r]
while {![eof $f]} {
    gets $f line
    append FILE_LIST "$line "
}
echo $FILE_LIST
close $f

#--------------------------Read Designs------------------------------
analyze -format $HDL $FILE_LIST 
#analyze -format sverilog $FILE_LIST -vcs "+define+xxx"
elaborate $TOP_DESIGN

#------------------------Set Current Design&&Link Designs------------
#current_design $TOP_DESIGN(auto)
#link(auto)

#-------------------------------SDC----------------------------------
source ../scripts/Sdc.tcl

#--------------------Map and Optimize the Design---------------------
compile_ultra -no_autoungroup -incremental -no_boundary_optimization
#----------------------Save Design Database--------------------------
change_names -rules $HDL -hierarchy
set_fix_multiple_port_nets -all -buffer_constants
#---------------Check the Synthesized Design for Consistency---------
check_design -summary > $SYN_ROOT_PATH/report/check_design.rpt
check_timing > $SYN_ROOT_PATH/report/check_timing.rpt
#---------------------Report Timing and Area-------------------------
report_qor                  > $SYN_ROOT_PATH/report/$TOP_DESIGN.qor_rpt
report_timing -max_paths 1000 > $SYN_ROOT_PATH/report/$TOP_DESIGN.timing_rpt
report_timing -path full    > $SYN_ROOT_PATH/report/$TOP_DESIGN.full_timing_rpt
report_timing -delay max    > $SYN_ROOT_PATH/report/$TOP_DESIGN.setup_timing_rpt
report_timing -delay min    > $SYN_ROOT_PATH/report/$TOP_DESIGN.hold_timing_rpt
report_reference            > $SYN_ROOT_PATH/report/$TOP_DESIGN.ref_rpt
report_area                 > $SYN_ROOT_PATH/report/$TOP_DESIGN.area_rpt
report_constraints          > $SYN_ROOT_PATH/report/$TOP_DESIGN.const_rpt
report_constraint -all_violators > $SYN_ROOT_PATH/report/$TOP_DESIGN.violators_rpt
report_power > $SYN_ROOT_PATH/report/$TOP_DESIGN.power_rpt
check_timing > $SYN_ROOT_PATH/last_check_timing.log
#---------------------Generate Files -------------------------
write_file -f ddc -hier -output $SYN_ROOT_PATH/unmapped/$TOP_DESIGN.ddc
write -f verilog -hierarchy -output $SYN_ROOT_PATH/mapped/$TOP_DESIGN.v
write_sdc $SYN_ROOT_PATH/mapped/$TOP_DESIGN.sdc
write_sdf -context verilog $SYN_ROOT_PATH/mapped/$TOP_DESIGN.sdf


    
